DocID025317 Rev 2

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STA333SML

Pin description

17

2.2

Pin list

Table 2. Pin description

Pin n°

Name

Description

Pad information

I/O pins

B4

LRCKI

I²S Left/Right clock

C4

BICKI

I²S serial clock

A5

SDI

I²S serial data channels 1 & 2

D5

XTI

Master clock input

E4

PWDN

-’0’ = power-down; ‘1’=normal operation

D4

INTLINE

-’0’ = power bridge in fault; ‘1’=normal operation

Power output pins

A2

OUT1A

Positive output 1

C1

OUT1B

Negative output 1

D1

OUT2A

Positive output 2

F2

OUT2B

Negative output 2

Power supplies (preliminary)

B2/C2

VCC1

Positive supply (upper MOSFET) to left H-bridge P output

E2/D2

VCC2

Positive supply (upper MOSFET) to right H-bridge P output

A1/B1

GND1

Negative supply (lower MOSFET) to left H-bridge P output

E1/F1

GND2

Negative supply (lower MOSFET) to right H-bridge P output

D3

These pins are output pins

that must be externally

filtered. Do not connect

these pins to external supply

voltage.

C3

GNDREG Reference voltage to ground

A4

VDDREG Reference voltage to 3.3 V

F4

VSS

B5

VDD_DIG Digital supply

C5

GND_DIG Digital ground

E5

VDD_PLL PLL supply

F5

GND_PLL PLL ground

A3, B3,

E3, F3

NC

Not connected