Electrical characteristics

STA533WF

6/15

Doc ID 17658 Rev 2

Test circuits

Figure 2.

Test circuit

Figure 3.

Current dead time test circuit

Table 7.

Logic truth table

Pin

PWRDN

Pin

TRISTATE

Inputs as per Figure 3

Transistors as per Figure 3

Output mode

INxA

INxB

Q1

Q2

Q3

Q4

0

0

x

x

Off

Off

Off

Off

Hi Z

1

1

0

0

Off

Off

On

On

Dump

1

1

0

1

Off

On

On

Off

Negative

1

1

1

0

On

Off

Off

On

Positive

1

1

1

1

On

On

Off

Off

Not used

Low current dead time = MAX(DTr,DTf)

OUTxY

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

t

DTf

DTr

Duty cycle = 50%

INxY

OUTxY

gnd

+Vcc

R 8

Ω

+

-

vdc = Vcc/2

D03AU1458

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

Rload=8

Ω

Q2

OUTxB

DTout(B)

DTin(B)

DTout(A)

470nF

470nF

470nF

Iout

Iout

Q4

Q1

Q3

INxB

D00AU1162_00

INxA

DTin(A)

Duty cycle=A

Duty cycle=B

Duty cycle A and B: Fixed to have DC output current of Iout in the direction shown in figure

22

μ

22

μ

OUTxA