14

ATSAM9708

1772D–DRMSD–01/04

External Memory Timing

Overview

master clock period is one-fourth of the clock period at X1. The internal master clock is

provided at pin CK_OUT when external SDRAM is connected (RAS sensed high during

RESET).

Basic notes on SDRAM timing:

•

RESET should be held low at least 100 µs (SDRAM timing requirement on idle

cycles)

•

SDRAM mode is fixed to sequential, burst length = 1, CAS latency 2, standard

operation, programmed write burst length.

•

SDRAM cycles for read: NOP - ACTIVE - NOP - READ AUTO PRECHARGE - NOP

- NOP.

•

SDRAM cycles for write: NOP - ACTIVE - NOP - WRITE AUTO PRECHARGE -

NOP - NOP

•

SDRAM cycles for refresh: NOP - AUTO REFRESH - NOP - NOP - NOP - NOP

Figure 5. ROM and SRAM Basic Timing, DRAM = Low

012345

012345

0

12345

0

1

CK_OUT

WA[26:0]

WOE

WWE

RBS

WD

[15:0]

ROM/SRAM16 READ

SRAM16 WRITE

SRAM8 WRITE