26

ATSAM9708

1772D–DRMSD–01/04

to 01FFH into the external DRAM space. The bootstrap then resumes control at

address 0100H.

•If PDWN is asserted low, then all I/Os and outputs will be floated and the crystal

oscillator and PLL will be stopped. The chip enters a deep power-down sleep mode.

To exit power down, PDWN has to be asserted high, then RESET applied.

Memory Type

Configuration and

Boot Configuration

At the end of power-up, when RESET input goes from low to high, RAS, CAS and

REFRESH pins are sampled by the ATSAM9708 to determine memory type configura-

tion and boot type. RAS, CAS and REFRESH must be pulled to V

external 10K resistor to select these different power-up configurations.

One memory type can be used for low pages (addresses [0-8000000h], AD[27] = 0) and

a different type for high pages (addresses [8000000h-10000000h]).

Memory types allowed are Flash/ROM, SRAM, DRAM or SDRAM.

When using RAM (SRAM, DRAM or SDRAM) in low page, P16 must start in bootstrap

state. When in bootstrap state, P16 program execution starts at address 0. If not in boot-

strap, program execution starts at address 100h. Bootstrap is selected via the

REFRESH pin.

Note:

1. When accessing DRAM or SDRAM, DRAM/SDRAM is selected by signals RAS and CAS (WCS0 and WCS1 are inactive)

and addresses are time-multiplexed on WA[..] pins as follows:

• WA0 - WA8: DRA0 - DRA8

• WA18: DRA9

• WA20: DRA10

• WA22: DRA11

When accessing SRAM, Flash or ROM, SRAM/Flash/ROM are selected by signals WCS0, WCS1 (RAS and CAS are inac-

tive) and WA[26:0] address pins:

• if low pages: WCS0 = 0, WCS1 = 1

• if high pages: WCS0 = 1, WCS1 = 0

Table 18. Memory Type and Boot Configuration

Pin Level Detected at Reset

Low Page

High Page

REFRESH

RAS

CAS

Memory Type

Selected by

Memory Type

Selected by

Stand-alone Mode

Low

Low

Low

Flash/ROM

WCS0

SRAM

WCS1

Low

Low

High

Flash/ROM

WCS0

DRAM

RAS, CAS

Low

High

Low

Flash/ROM

WCS0

SDRAM

RAS, CAS

Low

High

High

Flash/ROM

WCS0

Selected by firmware

Bootstrap Mode

High

Low

Low

SRAM

WCS0

Flash/ROM

WCS1

High

Low

High

DRAM

RAS, CAS

Flash/ROM

WCS1

High

High

X

SDRAM

RAS, CAS

Flash/ROM

WCS1