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AM79C875KC 数据表(PDF) 19 Page - Advanced Micro Devices |
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AM79C875KC 数据表(HTML) 19 Page - Advanced Micro Devices |
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19 / 48 page ![]() Am79C875 19 signal on the first NLP. It locks the polarity correction circuitry after the reception of two consecutive packets. The state of the polarity correction circuitry is locked as long as link is established. This function is only avail- able in 10BASE-T mode. Far-End Fault Indication (FEFI) Auto-Negotiation provides a remote fault capability for dete c tin g an asym me tric lin k fa ilur e. Since 100BASE-FX systems do not use Auto-Negotiation, an alternative, in-band signaling scheme is used to signal remote fault conditions. This scheme, Far End Fault In- dication, relies on the characteristics of the quiescent state, a continuous IDLE stream. The IDLE stream is a continuous stream of logic ones followed by one logic zero, with the pattern repeated at least 3 times. A Far-End Fault will be signaled under the following three conditions: (1) When no activity is received from the link partner, since this can indicate a broken receive wire, (2) When the clock recovery circuit detects a receive signal error or PLL lock error, (3) When man- agement entity sets the transmit Far-end fault bit (Register 24, bit 7). The Far-End fault mechanism defaults to enabled in 100BASE-FX mode and disabled in 100BASE-TX and 10BASE-T modes, and may be controlled by software after reset. MLT-3 This block is responsible for converting the NRZI data stream from the PDX block to the MLT-3 encoded data stream. The effect of MLT-3 is the reduction of energy on the copper media (TX or FX cable) in the critical frequency range of 1 MHz to 100 MHz. The receive section of this block is responsible for equalizing and amplifying the received data stream and link detection. The adaptive equalizer compensates for the amplitude and phase distortion due to the cable. MLT-3 is a tri-level signal. All transitions are between 0 V and +1 V or 0 V and -1 V. A transition has a logical value of 1 and a lack of a transition has a logical value of 0. The benefit of MLT-3 is that it reduces the maxi- mum frequency over the data line. The bit rate of TX data is 125 Mbps. The maximum frequency (using NRZI) is half of 62.5 MHz. MLT-3 reduces the maxi- mum frequency to 31.25 MHz. A data signal stream following MLT-3 rules is illustrated in Figure 6. The data stream is 1010101. MLT-3 1010101 8 ns 22236G-8 Figure 6. MLT-3 Waveform The TX± drivers convert the NRZI serial output to MLT-3 format. The RX± receivers convert the received MLT-3 signals to NRZI. The transmit and receive sig- nals will be compliant with IEEE 802.3u, Section 25. The required signals (MLT-3) are described in detail in ANSI X3.263:1995 TP-PMD Revision 2.2 (1995). The NetPHY™ 4LP device provides on-chip filtering. External filters are not required for either the transmit or receive signals. The TX± pins can be connected to the media via either a 1:1 transformer or a 1.25:1 transformer. The 1.25:1 ratio provides a 20% transmit power savings over the 1:1 ratio. Refer to Figure 7. Adaptive Equalizer The NetPHY™ 4LP device is designed for the maxi- mum of 140 meter UTP-5 cable. A 140-meter UTP-5 cable attenuates the signal by 32 dB at 100 MHz which far exceed the cable plant attenuation (24-26 dB) de- fined by TP-PMD. The amplitude and phase distortion from cable causes inter-symbol interference (ISI) which makes clock and data recovery impossible. Adaptive equalization is done by closely matching the characteristics of the twisted-pair cable. This is a variable equalizer which changes equalizer frequency response in accordance with cable length. The cable length is estimated based on comparisons of incoming signal strength against some known cable characteristics. The equalizer tunes itself automatically to the any cable length to compen- sate for the amplitude and phase distortion incurred from the cable. Baseline Wander Compensation The 100BASE-TX data stream is not always DC bal- anced. The media, with transformer and common |
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