AM79C875KC datasheet(13/48 Pages) AMD

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Am79C875

FUNCTIONAL DESCRIPTION

Overview

The NetPHY™ 4LP transceiver is a four-port CMOS

device that implements the complete physical layer for

10BASE-T and the Physical Coding Sublayer (PCS),

Physical Medium Attachment (PMA), and Physical Me-

dium Dependent (PMD) functionality for 100BASE-TX.

The NetPHY™ 4LP transceiver implements Auto-Ne-

gotiation allowing two devices connected across a link

segment to take maximum advantage of their capabili-

ties. Auto-Negotiation is performed as defined in the

IEEE 802.3u specification.

The NetPHY™ 4LP device communicates with a

switch or MAC device through the Reduced Media In-

dependent Interface (RMII).

The NetPHY™ 4LP device consists of the following

functional blocks:

■ RMII Functional Blocks

■ 100BASE-X Block including:

— Transmit and Receive State Machines

— 4B/5B Encoder and Decoder

— Stream Cipher Scrambler and Descrambler

— Link Monitor State Machine

— Far End Fault Indication (FEFI) State Machine

— MLT-3 Encoder

— MLT-3 Decoder with adaptive equalization

■ 10BASE-T Block including:

— Manchester Encoder/Decoder

— Jabber

— Receive Polarity Detect

— Waveshaping and Filtering

■ Carrier Integrity Monitor

■ Auto-Negotiation

■ Status LEDs

■ PHY Control and Management

Modes of Operation

The RMII interface provides the data path connection

between the NetPHY™ 4LP transceivers and the

Media Access Controller (MAC), repeater, or switch de-

vices. The MDC and MDIO pins are responsible for

communication between the NetPHY™ 4LP trans-

ceiver and the station management entity (STA).

The RMII standard reduces the pin count by halving the

number of data pins, eliminating pins not used in switch

applications, and using a single global clock. Each port

has an independent RMII.

RMII uses seven pins per port. They are as follows:

Receive Data

RXD[X]_[1:0]

Carrier Sense

CRS_DV[X]

Receive Error

RX_ER[X]

Transmit Data

TXD[X]_[1:0]

Transmit Enable

TX_EN[X]

Note: [X] refers to the port.

In RMII mode, REF_CLK must be sourced by a

50-MHz clock signal.

RMII Pin Descriptions

CRS_DV

Carrier Sense/Receive Data Valid

CRS_DV is asserted by the PHY when the receive me-

dium is non-idle. Loss of carrier results in the deasser-

tion of CRS_DV synchronous to the cycle of REF_CLK,

which presents the first di-bit of a nibble onto RXD[1:0]

(i.e., CRS_DV is deasserted only on nibble bound-

aries). If the PHY has additional bits to be presented on

RXD[1:0] following the initial deassertion of CRS_DV,

the PHY asserts CRS_DV on cycles of REF_CLK

which present the second di-bit of each nibble. The

PHY deasserts CRS_DV on cycles of REF_CLK which

present the first di-bit of the nibble. As a result, starting

on the byte boundaries, CRS_DV toggles at 25 MHz in

100 Mbps mode and 2.5 MHz in 10 Mbps mode when

CRS ends before RX_DV (i.e., the FIFO still has bits to

transfer when the carrier event ends). Therefore, the

MAC can accurately recover RX_DV and CRS. Refer

to Figure 1.

During a false carrier event, CRS_DV remains as-

serted for the duration of carrier activity. Refer to

Figure 2.

The data on RXD[1:0] is considered valid once

CRS_DV is asserted. However, since the assertion of

CRS_DV is asynchronous relative to REF_CLK, the

data on RXD[1:0] is “00” until proper receive signal

decoding takes place.

Note: CRS_DV is asserted asynchronously in order

to minimize latency of control signals through the PHY.

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