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L5973AD

3.5 ERROR AMPLIFIER

The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose

non inverting input is connected to the internal voltage reference (1.235V), while the inverting input (FB) is con-

nected to the external divider or directly to the output voltage. The output (COMP) is connected to the external

compensation network.

The uncompensated error amplifier has the following characteristics:

The error amplifier output is compared with the oscillator sawtooth to perform PWM control.

3.6 PWM COMPARATOR AND POWER STAGE

This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM

signal for the driving stage.

The power stage is a very critical block cause it has to guarantee a correct turn on and turn off of the PD-

MOS.

The turn on of the power element, or better, the rise time of the current at turn on, is a very critical param-

eter to compromise.

At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses.

But there is a limit introduced by the recovery time of the recirculation diode.

In fact when the current of the power element equals the inductor current, the diode turns off and the drain

of the power is free to go high. But during its recovery time, the diode can be considered as an high value

capacitor and this produces a very high peak current, responsible of many problems:

Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics.

Turn on overcurrent causing a decrease of the efficiency and system reliability.

Big EMI problems.

Shorter freewheeling diode life.

The fall time of the current during the turn off is also critical. In fact it produces voltage spikes (due to the

parasitics elements of the board) that increase the voltage drop across the PDMOS.

In order to minimize all these problems, a new topology of driving circuit has been used and its block dia-

gram is shown in fig. 8.

The basic idea is to change the current levels used to turn on and off the power switch, according with the

PDMOS status and with the gate clamp status.

This circuitry allow to turn off and on quickly the power switch and to manage the above question related

to the freewheeling diode recovery time problem. The gate clamp is necessary to avoid that Vgs of the

internal switch goes higher than Vgsmax. The ON/OFF Control block avoids any cross conduction be-

tween the supply line and ground.

Transconductance

2300

µS

Low frequency gain

65dB

Minimum sink/source voltage

1500

µA/300µA

Output voltage swing

0.4V/3.65V

Input bias current

2.5

µA