L5973AD

6/14

Figure 6. Oscillator Circuit

3.4 CURRENT PROTECTION

The L5973AD has two current limit protections, pulse by pulse and frequency fold back.

The schematic of the current limitation circuitry for the pulse by pulse protection is shown in figure 7.

The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a resistor in series,

PDMOS is switched off until the next falling edge of the internal clock pulse.

Due to this reduction of the ON time, the output voltage decreases.

Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not enough to obtain a suf-

ficiently low duty cycle at 500KHz, the output current, in strong overcurrent or short circuit conditions, could in-

crease again. For this reason the switching frequency is also reduced, so keeping the inductor current under its

maximum threshold. The Frequency Shifter (see fig. 6) depends on the feedback voltage. As the feedback volt-

age decreases (due to the reduced duty cycle), the switching frequency decreases too.

Figure 7. Current Limitation Circuitry

FREQUENCY

SHIFTER

CLOCK

GENERATOR

RAMP

GENERATOR

SYNCHRONIZATOR

CLOCK

RAMP

Ibias_osc

SYNC

t

D00IN1131

DRIVER

NOT

A1

PWM

VCC

OUT

A1/A2=95

RSENSE

D00IN1134

I

I

RTH

A2