TSV62X datasheet(5/24 Pages) STMICROELECTRONICS

5 / 24 page

DocID15689 Rev 6

5/24

TSV62x, TSV62xA

Electrical characteristics

Table 4.

Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C,

and RL connected to VCC/2 (unless otherwise specified)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

DC performance

Vio

Offset voltage

TSV62x

TSV62xA

TSV623AIST - MiniSO10

0.8

TSV62x -Tmin < Top < Tmax

TSV62xA - Tmin < Top < Tmax

TSV623AIST - Tmin < Top < Tmax

2.2

ΔVio/ΔT Input offset voltage drift

μV/°C

Iio

Input offset current

(Vout = VCC/2)

10 (1)

Tmin < Top < Tmax

1100

Iib

Input bias current

(Vout = VCC/2)

10 (1)

Tmin < Top < Tmax

1100

CMR

Common mode rejection

ratio 20 log (

ΔVic/ΔVio)

0 V to 1.8 V, Vout = 0.9 V

Tmin < Top < Tmax

Avd

Large signal voltage gain

RL= 10 kΩ, Vout= 0.5 V to 1.3 V

Tmin < Top < Tmax

VOH

High level output voltage

(VOH = VCC - Vout)

RL = 10 kΩ

Tmin < Top < Tmax

535

VOL

Low level output voltage

RL = 10 kΩ

Tmin < Top < Tmax

435

Iout

Isink

Vout = 1.8 V

Tmin < Top < Tmax

Isource

Vout = 0 V

Tmin < Top < Tmax

ICC

Supply current (per operator)

No load, Vout =VCC/2

µA

Tmin < Top < Tmax

AC performance

GBP

Gain bandwidth product

RL = 10 kΩ, CL = 100 pF, f = 100 kHz

275

340

kHz

Unity gain frequency

RL = 10 kΩ, CL = 100 pF,

280

φm

Phase margin

Degrees

Gain margin

Slew rate

RL = 10 kΩ, CL = 100 pF, Av=1

0.1

0.155

μs

1. Guaranteed by design.

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