2

PS8545 06/20/01

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PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

FunctionTable

s

t

u

p

n

Is

t

u

p

t

u

Oe

t

a

t

S

L

L

P

V

D

K

L

CK

L

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4

:

0

[

Y]

4

:

0

[

YT

U

O

B

FT

U

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D

N

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H

Z

Z

Z

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ff

O

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p

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B

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N

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L

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B

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V

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n

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H

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H

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n

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)

m

o

n

(

V

5

.

2z

H

M

0

2

<Z

Z

Z

Z

ff

o

Notes: For testing and power saving purposes, PI6CV855 will power down if the frequency of the reference inputs

CLK, CLK is well below the operating frequency range. The maximum power down clock frequency is below 20 MHz.

For example, PI6CV855 will be powered down when the CLK,CLK stop running.

Z = High impedance

X = Don’t care

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PinoutTable