3

PS8545 06/20/01

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PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

Note: Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

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Notes:

1. The PLL is able to handle spread spectrum induced skew.

2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is

not required to meet the other timing parameters. (Used for low-speed debug).

3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.

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