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S3A3 数据表(PDF) 91 Page - Renesas Technology Corp |
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S3A3 数据表(HTML) 91 Page - Renesas Technology Corp |
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91 / 139 page  R01DS0307EU0100 Rev.1.00 Page 91 of 139 Mar 7, 2017 S3A3 2. Electrical Characteristics 2.3.12 IIC Timing Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle Note 1. The value in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1. Table 2.42 IIC timing Conditions: VCC = 2.7 to 5.5 V Parameter Symbol Min*1 Max Unit Test conditions IIC (standard mode, SMBus) SCL input cycle time tSCL 6 (12) × tIICcyc + 1300 - ns Figure 2.70 SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time tSr - 1000 ns SCL, SDA input fall time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 -ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1 (5) × tIICcyc + tPcyc + 300 -ns Repeated START condition input setup time tSTAS 1000 - ns STOP condition input setup time tSTOS 1000 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0- ns SCL, SDA capacitive load Cb - 400 pF IIC (Fast mode) SCL input cycle time tSCL 6 (12) × tIICcyc + 600 - ns Figure 2.70 For all ports except P408, use PmnPFS.DS CR of middle drive. For port P408, use PmnPFS.DS CR1/DSCR of middle drive for IIC fast-mode. SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time tSr - 300 ns SCL, SDA input fall time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 -ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1(5) × tIICcyc + tPcyc + 300 -ns Repeated START condition input setup time tSTAS 300 - ns STOP condition input setup time tSTOS 300 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0- ns SCL, SDA capacitive load Cb - 400 pF |
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