Technical information

USBUF

6/13

DocID7041 Rev 8

Figure 6. USBUF ESD clamping behavior

Figure 7. Measurement board

To have a good approximation of the remaining voltages at both Vin and Vout stages, we

give the typical dynamical resistance value Rd. By taking into account these following

Vinput = 31.2 V

Voutput = 7.95 V

This confirms the very low remaining voltage across the device to be protected. It is also

important to note that in this approximation the parasitic inductance effect was not taken into

The measurements done hereafter show very clearly (figure 8) the high efficiency of the

ESD protection:

•

no influence of the parasitic inductances on Voutput stage

•

ESD Surge

Vinput

Voutput

Rload

Rg

Rt

S1

Rd

V

BR

V

BR

V

PP

Device

to be

protected

USBUF01W6

Rd

S2

TEST BOARD

ESD

SURGE

16kV

Air

Discharge

Vin

Vout

Vinput

R

g

V

BR

⋅

R

d

V

g

⋅

+

R

g

-----------------------------------------------

=

V

ouput

R

t

V

BR

⋅

R

d

Vinput

⋅

+

R

t

-------------------------------------------------------

=