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WM9705 数据表(PDF) 39 Page - Wolfson Microelectronics plc |
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WM9705 数据表(HTML) 39 Page - Wolfson Microelectronics plc |
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39 / 55 page  WM9705 Production Data w PD Rev 4.0 December 2003 39 SERIAL INTERFACE REGISTER MAP The following table shows the function and address of the various control bits that are loaded and read through the serial interface. Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 6150h 02h Master volume Mute X X ML4 ML3 ML2 ML1 ML0 X X X MR4 MR3 MR2 MR1 MR0 8000h 04h HPHONE volume Mute X X ML4 ML3 ML2 ML1 ML0 X X X MR4 MR3 MR2 MR1 MR0 8000h 06h Master volume mono Mute X X X X X X X X X X MM4 MM3 MM2 MM1 MM0 8000h 0Ah PCBEEP volume Mute X X X X X X X X X X PV3 PV2 PV2 PV0 X 8000h 0Ch Phone volume Mute X X X X X X X X X X GN4 GN3 GN2 GN1 GN0 8008h 0Eh Mic volume Mute X X X X X X X X 20dB X GN4 GN3 GN2 GN1 GN0 8008h 10h Line in volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h 12h CD volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h 14h Video volume Mute X X 0 1 0 0 0 X X X 0 1 0 0 0 8808h 16h Aux volume Mute X X 0 1 0 0 0 X X X 0 1 0 0 0 8808h 18h PCM out volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h 1Ah Rec select X X X X X SL2 SL1 SL0 X X X X X SR2 SR1 SR0 0000h 1Ch Rec gain Mute X X X GL3 GL2 GL1 GL0 X X X X GR3 GR2 GR1 GR0 8000h 20h General purpose POP X 3D X X X MIX MS LPBK X X X X X X X 0000h 22h 3D control X X X X X X X X X X X X DP3 DP2 DP1 DP0 0000h 26h Power/down control status APD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Fh 28h Ext’d audio ID ID1 ID0 X X REV1 REV0 AMAP LDAC SDAC CDAC DSA1 DSA0 VRM SPDIF DRA VRA 0605h 2Ah Ext’d audio stat/ctrl X X X X X SPCV X X X X SPSA1 SPSA0 X SPDIF X VRA 0000h 2Ch Audio DAC rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h 32h Audio ADC rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h 3Ah SPDIF control V 0 1 0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY UDIB PRO 2000h 5Ah Mixer Path Mute 0 0 0 0 0 0 0 0 0 0 0 MPM 0 0 0 0 0000h 5Ch Add. Function control AMUTE HSCP PUEN MHPZ PSEL HSEN HSDT HPND AMEN I2S ADCN DAC ADCO HPF HS CMP ASS1 ASS0 0000h 72h Front mixer volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 0808h 74h Add. Function X X X X X X X X X X X X HPB I2S64 X MONOEN 0000h 76h Digitizer control POLL ADR2 ADR1 ADR0 COO CTC CR1 CR0 DEL3 DEL2 DEL1 DEL0 SLEN SLT2 SLT1 SLT0 0006h 78h Digitizer control PRP1 PRP0 RPR PDEN PINV BSEN BINV WAIT PIL PHIZ MSK1 MSK0 PDD3 PDD2 PDD1 PDD0 0000h 7Ah Pen Digitizer data PNDN ADR2 ADR1 ADR0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0000h 7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 574Dh 7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1 Rev0 4C05h Table 23 Serial Interface Register Map Description Note: 1. Default values of register 28h and 2Ah depend on whether the device is a primary or secondary, and whether SPDIF capability is enabled by pulling pin 44 SPEN high. The conditions shown are for a primary codec with SPDIF capability. 2. Register 5Ah is write only. When writing to this register all bits except MPM (bit 4) must be written as 0, otherwise device function can not be guaranteed. |
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