HT82K94E/HT82K94A

Rev. 2.40

21

November 5, 2014

MISC register combines a command and status to control desired endpoint FIFO action and to show the status of the

desired endpoint FIFO. The MISC will be cleared by USB reset signal.

Bit No.

Label

R/W

Function

0

REQ

R/W

After setting the other status of the desired one in the MISC, endpoint FIFO can be

requested by setting this bit to

²1². After the job has been done, this bit has to be

cleared to

²0².

1

TX

R/W

This bit defines the direction of data transferring between MCU and endpoint FIFO.

When the TX is set to

²1², this means that the MCU wants to write data to the end-

point FIFO. After the job has been done, this bit has to be cleared to

²0² before termi-

nating request to represent the end of transferring. For reading action, this bit has to

be cleared to

²0² to represent that MCU wants to read data from the endpoint FIFO

and has to be set to

²1² after the job is done.

2

CLEAR

R/W

Clear the requested endpoint FIFO, even if the endpoint FIFO is not ready.

4

3

SELP1

SELP0

R/W

Defines which endpoint FIFO is selected, SELP1,SELP0:

00: endpoint FIFO0

01: endpoint FIFO1

10: endpoint FIFO2

11: endpoint FIFO3

5

SCMD

R/W

Used to show that the data in endpoint FIFO is a SETUP command. This bit has to

be cleared by firmware. That is to say, even the MCU is busy, the device will not miss

any SETUP commands from the host.

6

READY

R

Read only status bit, this bit is used to indicate that the desired endpoint FIFO is

ready to work.

7

LEN0

R/W

Used to indicate that a 0-sized packet is sent from a host to the MCU. This bit should

be cleared by firmware.

MISC (46H) Register

The MCU can communicate with the endpoint FIFO by setting the corresponding registers, of which address is listed in

the following table. After reading the current data, next data will show after 2

ms, used to check the endpoint FIFO status

and response to MISC register, if read/write action is still going on.

Registers

R/W

Bank

Address

Bit7~Bit0

FIFO0

R/W

1

48H

Data7~Data0

FIFO1

R/W

1

49H

Data7~Data0

FIFO2

R/W

1

4AH

Data7~Data0

FIFO3

R/W

1

4BH

Data7~Data0

There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading,

writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing

and clearing.

Actions

MISC Setting Flow and Status

Read FIFO0 sequence

00H

®01H®delay 2ms, check 41H®read* from FIFO0 register and

check not ready (01H)

®03H®02H

Write FIFO1 sequence

0AH

®0BH®delay 2ms, check 4BH®write* to FIFO1 register and

check not ready (0BH)

®09H®08H

Check whether FIFO0 can be read or not

00H

®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H

Check whether FIFO1 can be written or not

0AH

®0BH®delay 2ms, check 4BH (ready) or 0BH (not ready)®0AH

Read 0-sized packet sequence form FIFO0

00H

®01H®delay 2ms, check 81H®read once (01H)®03H®02H

Write 0-sized packet sequence to FIFO1

0AH

®0BH®delay 2ms, check 0BH®0FH®0DH®08H

Note:

*: There are 2

ms existing between 2 reading action or between 2 writing action