USB97CFDC datasheet(8/20 Pages) SMSC

8 / 20 page

SMSC DS – USB97CFDC

Page 8

Rev. 12/15/2000

PIN NO.

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

DRVDEN 0

OD12

An active low on this pin indicates a disk drive

spindle speed change from 300 RPM to 360 RPM

or 1.2M format disks in three mode drives. This

pin should be tied to the disk drives spindle speed

control input pin.

DRVDEN 1

DRVDEN1

OD12

Reserved for future use.

Write Gate

nWGATE

OD12

This active low high current driver allows current to

flow through the write head. It becomes active just

prior to writing to the diskette.

Track 0

nTRK0

This active low Schmitt Trigger input senses from

the disk drive that the head is positioned over the

outermost track.

Index

nINDEX

This active low Schmitt Trigger input senses from

the disk drive that the head is positioned over the

beginning of a track, as marked by an index hole.

Write Protect nWRTPRT

This active low Schmitt Trigger input senses from

the disk drive that a disk is write protected. Any

write command is ignored.

Motor On 0

nMTR0

OD12

This active low open drain output selects motor

drive 0.

Drive Select 0 nDS0

OD12

This active low open drain output selects drive 0.

USB INTERFACE

USB Bus

Data

USB-

USB+

IO-U

These pins connect to the USB data signals

through 33 ohm series resistors. The USB+ line

should be pulled up with a 5%, 1.5K ohm resistor

to indicate that this is a high speed USB device.

USB

Transceiver

Supply

AVDD

This is the 3.3V supply to the internal USB

transceiver.

USB

Transceiver

Ground

AGND

This is the supply ground for the internal USB

transceiver.

FLASH INTERFACE

31-38

Flash Memory

Data Bus

FD[7:0]

IO8

These signals are used to transfer data between

the internal 8051 and the external FLASH program

memory.

50, 53, 54,

49, 57, 29,

56, 55, 48-

44, 42-40,

Flash Memory

Address Bus

FA[15:0]

These signals address memory locations within

the FLASH memory.

Flash Memory

Read Strobe

nFRD

Flash ROM Read; active low

Flash Memory

Chip Select

nFCE

Flash ROM Chip Select; active low

SRAM/IO INTERFACE

1-7,

9-13,

99,100

SRAM

Memory Bus

SA[13:0]

These signals provide the memory address to an

external SRAM buffer.

84-87,

89-92

SRAM

Memory Data

Bus

SD[7:0]

I/O8

These signals are used to transfer data to/from the

SRAM Memory.

SRAM

Memory Read

Strobe

nMEMR

Memory read; active low

This active low signal indicates that data is to be

driven onto the data bus by the SRAM. Data will

be latched internal to the chip on the rising edge of

this signal

SRAM

Memory Write

Strobe

nMEMW

Memory write; active low

This active low signal indicates to the SRAM to

load data from the data bus on its rising edge.

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