USB97CFDC datasheet(9/20 Pages) SMSC

9 / 20 page

SMSC DS – USB97CFDC

Page 9

Rev. 12/15/2000

PIN NO.

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

MISCELLANEOUS

Crystal

Input/External

Clock Input

XTAL1/

CLKIN

ICLKx

14.318Mhz Crystal or clock input.

This pin can be connected to one terminal of the

crystal or can be connected to an external

14.318Mhz clock when a crystal is not used.

Crystal

Output

XTAL2

OCLKx

14.318Mhz Crystal

This is the other terminal of the crystal, or left

open when an external clock source is used to

drive XTAL1/CLKIN. It may not be used to drive

any external circuitry other than the crystal circuit.

SRAM Enable nMEMEN

O24

An active low signal is output on this pin to enable

the optional external SRAM for extended FDC

write and read caching for ultra high performance

applications.

Option Enable OPTEN

Current

firmware

utilizes

this

input

for

detecting the media density switch of the drive.

Various firmware options are available for different

polarities of this signal.

Contact

factory

for

available firmware options. If this pin is not driven

by the drive, it should be tied low.

Drive Ready

nDRVRDY

An active low signal on this pin from the floppy

disk drive, after DS0 goes active, indicates that

the system may activate MTR0. If the drive does

not supply this signal, this pin should be tied low.

Drive Power

nFDPWR

OD24

This active low signal is intended to activate an

external power switch, either in the drive or on the

system board, to supply power to the floppy disk

drive. It is active whenever the USB97CFDC is not

in SUSPEND mode.

RESET input

nRESET

This active low signal is used by the system to

reset the chip. The active low pulse should be at

least 100ns wide.

Test output

TSTOUT

This signal is used for testing the chip via an

internal XNOR chain. User should normally leave

it unconnected.

Test input

nTEST

This signal is a manufacturing test pin. It should

be tied to VDD for normal operation.

Test Enable

nTESTEN

This active low signal places the device into board

test mode using the XNOR chain. For normal

operation this pin should be tied high. See Board

Test Mode Operation on page 10

POWER, GROUND, AND NO CONNECTS

14, 39, 60,

82, 93

VDD

+3.3V power

8, 19, 27, 43,

52, 66, 79,

81, 88

GND

Ground Reference

20, 51, 78,

80, 83, 94-96

No Connect. These pins should not be connected

externally.

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