16

DS734F5

5.15 Switching Characteristics—Digital Audio Output (DAO) Port

5.15 Switching Characteristics—Digital Audio Output (DAO) Port

Figure 5-9. Digital Audio Output Port Timing, Master Mode

Parameter

Symbol

Min

Max

Unit

DAO_MCLK period

40

—

ns

DAO_MCLK duty cycle

—

45

55

%

1.Master mode timing specifications are characterized, not production tested.

40

—

ns

—40

60

%

1.Master mode timing specifications are characterized, not production tested.

2.Master mode is defined as the CS48xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_

LRCLK.

Parameter

Symbol

Min

Max

Unit

DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input

—19

ns

3.This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid.

—8

ns

—8

ns

—10

ns

DAO_MCLK

DAO_SCLK

DAO_LRCLK

DAOn_DATAn

Note:

In these diagrams, Falling edge is the inactive edge of DAO_SCLK.