CDCV855, CDCV855I

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002

3

POST OFFICE BOX 655303

–0.5 V to 3.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

105.8

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–

65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 3.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN

TYP

MAX

UNIT

Supply voltage, VDDQ, AVDD

2.3

2.7

V

Low level input voltage V

CLK, CLK, FBIN, FBIN

VDDQ/2 – 0.18

V

Low-level input voltage, VIL

PWRDWN

–0.3

0.7

V

High level input voltage V

CLK, CLK, FBIN, FBIN

VDDQ/2 + 0.18

V

High-level input voltage, VIH

PWRDWN

1.7

VDDQ + 0.3

V

DC input signal voltage (see Note 5)

–0.3

VDDQ

V

Differential input signal voltage, VID (see Note 6)

CLK, FBIN

0.36

VDDQ + 0.6

V

Output differential cross-voltage, VO(X) (see Note 7)

VDDQ/2 – 0.2 VDDQ/2

VDDQ/2 + 0.2

V

Input differential pair cross-voltage, VI(X) (see Note 7)

VDDQ/2 – 0.2

VDDQ/2 + 0.2

V

High-level output current, IOH

–12

mA

Low-level output current, IOL

12

mA

Input slew rate, SR (see Figure 7)

1

4

V/ns

Operating free air temperature TA

Commercial

0

85

°C

Operating free-air temperature, TA

Industrial

–40

85

°C

NOTES:

4. Unused inputs must be held high or low to prevent them from floating.

5. DC input signal voltage specifies the allowable dc execution of differential input.

6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level

and VCP is the complementary input level.

7. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be

crossing.