MDS 601-01 L

2

Revision 111204

ICS601-01

Pin Assignment

Multiplier Select Table

0 = connect directly to ground

1 = connect directly to VDD

Pin Descriptions

1

2

3

VDD

4

REFEN

5

6

GND

7

8

GND

REFOUT

S3

S1

GND

X2

S2

VDD

16

CLK

VDD

X1/ICLK

S0

OE

15

14

13

12

11

10

9

16 Pin (150 mil) TSSOP or SOIC

S3

S2

S1 S0

CLK (see note 2 on following page)

00

0

0

TEST

00

0

1

TEST

00

1

0

Input x1

00

1

1

Input x3

01

0

0

Input x4

01

0

1

Input x5

01

1

0

Input x6

01

1

1

Input x8

10

0

0

TEST

10

0

1

Crystal osc. pass through (no PLL)

10

1

0

Input x2

10

1

1

TEST

11

0

0

Input x8

11

0

1

Input x10

11

1

0

Input x12

11

1

1

Input x16

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

CLK

Output

Clock output from VCO. Output frequency equals the input frequency times multiplier.

2

REFEN

Input

Reference clock enable. Turns off the buffered crystal oscillator clock (stops low) when low.

3

VDD

Power

Connect to +3.3V or +5V. Must match other VDDs.

4

VDD

Power

Connect to +3.3V or +5V. Must match other VDDs.

5

VDD

Power

Connect to +3.3V or +5V. Must match other VDDs.

6

X2

XO

Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.

Leave disconnected for an external clock input.

7

S1

Input

Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.

8

X1/ICLK

XI

Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal or clock.

9

S2

Input

Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.

10

S3

Input

Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.

11

S0

Input

Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.

12

OE

Input

Output Enable. Tri-states both output clocks when low. Internal pull-up.

13

REFOUT

Output

Buffered crystal oscillator clock output. Controlled by REFIN.

14 - 16

GND

Power

Connect to ground.