ICS60101 datasheet(1/8 Pages) ICST

部件名	ICS60101

功能描述	LOW PHASE NOISE CLOCK MULTIPLIER

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制造商	ICST [Integrated Circuit Systems]

网页	http://www.icst.com

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ICS601-01

MDS 601-01 L

1

Revision 111204

Integrat ed Circuit Systems ● 525 Race Stre et, San Jo se, CA 9 5126 ● te l (40 8 ) 2 97-12 01 ● www.ics t.co m

LOW PHASE NOISE CLOCK MULTIPLIER

Description

The ICS601-01 is a low-cost, low phase noise,

high-performance clock synthesizer for applications

which require low phase noise and low jitter. It is ICS’

lowest phase noise multiplier, and also the lowest

CMOS part in the industry. Using ICS’ patented

analong and digital Phase-Locked Loop (PLL)

techniques, the chip accepts a 10 - 27 MHz crystal or

clock input, and produces output clocks up to 156 MHz

at 3.3 V.

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input

and output skew and jitter are not defined nor

guaranteed. For applications which require definted

input to output timing, use the ICS670-01.

Features

• Packaged in 16-pin SOIC or TSSOP

• Available in Pb (lead) free package

• Uses fundamental 10 - 27 MHz crystal or clock

• Patented PLL with the lowest phase noise

• Output clocks up to 156 MHz at 3.3 V

• Low phase noise: -132 dBc/Hz at 10 kHz

• Low jitter - 18 ps one sigma typ.

• Full swing CMOS outputs with 25 mA drive capability

at TTL levels

• Advanced, low power, sub-micron CMOS process

• Industrial temperature range available

• Operating voltage of 3.3V or 5V

Block Diagram

ROM Based

Multipliers

VCO

Divide

X1/ICLK

X2

Crystal or

clock input

Crystal

Oscillator

Reference

Divider

Phase

Comparator

Charge

Pump

Loop

Filter

VCO

S3:0

GND

3

4

VDD

3

CLK

REFOUT

REFEN

OE

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