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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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IRCC 数据表(PDF) 68 Page - SMSC Corporation |
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IRCC 数据表(HTML) 68 Page - SMSC Corporation |
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68 / 79 page  68 Burst (Demand) Mode DMA Burst mode is enabled by setting the DMA Burst bit in SCE Configuration Register B. Demand Mode DMA transfers up to 32 data bytes for each DRQ (Figure 37). The IrCC guarantees that DRQ relinquishes the ISA bus after thirty-two DMA I/O read or write cycles to allow for memory refresh. 32 I/Ox Clock DMA Refresh Counter The 32 I/Ox Clock DMA Refresh Counter is used to prevent DRQ from staying active for more than 32 I/O read/write cycles at a time. The counter is stopped and preloaded whenever DRQ is not active. Once DRQ becomes active, the counter decrements until zero-count or DRQ is deactived. In Demand Mode, the count-zero condition always clears DRQ and triggers a Refresh Interval. The Refresh Interval remains active for 350ns following an inactive nDACK (Figure 38). If there is more data to transfer, DRQ goes active again and the cycle repeats. Single Byte Mode DMA does not use the 32 I/Ox Clock Refresh Counter. DM A En a b l e DR Q I/O x n DAC K DM A Bu r s t AE N TC FIGURE 37 - DMA BURST MODE TIMING |
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