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HC652 数据表(PDF) 5 Page - System Logic Semiconductor

部件名 HC652
功能描述  Octal 3-State Bus Transceivers and D Flip-Flops
PDF  9 Pages
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制造商  SLS [System Logic Semiconductor]
网页  http://www.slsemicon.co.kr/e_index.htm
标志 SLS - System Logic Semiconductor

HC652 数据表(HTML) 5 Page - System Logic Semiconductor

  HC652 Datasheet HTML 1Page - System Logic Semiconductor HC652 Datasheet HTML 2Page - System Logic Semiconductor HC652 Datasheet HTML 3Page - System Logic Semiconductor HC652 Datasheet HTML 4Page - System Logic Semiconductor HC652 Datasheet HTML 5Page - System Logic Semiconductor HC652 Datasheet HTML 6Page - System Logic Semiconductor HC652 Datasheet HTML 7Page - System Logic Semiconductor HC652 Datasheet HTML 8Page - System Logic Semiconductor HC652 Datasheet HTML 9Page - System Logic Semiconductor  
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SL74HC652
System Logic
Semiconductor
SLS
TIMING REQUIREMENTS(Input t
r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to-55°C
≤85°C
≤125°C
Unit
tsu
Minimum Setup Time, Input A to
A-to-B Clock (or Input B to B-to-A
Clock) (Figure 7)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
th
Minimum Hold Time, A-to-B Clock to
Input A (or B-to-A Clock to
Input B) (Figure 7)
2.0
4.5
6.0
25
5
5
30
6
5
40
8
7
ns
tw
Minimum Pulse Width, A-to-B Clock
(or B-to-A Clock)
(Figure 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tr, tf
Maximum Input Rise and Fall Times
(Figures 2 and 3)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
TIMING DIAGRAM



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