TA 235

2/6

Figure 2. Firmware Hub Read Protocol

Figure 3. Firmware Hub Write Protocol

AI03437

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START

IDSEL

ADDR

MSIZE

TAR

SYNC

DATA

TAR

11712322

AI03441

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START

IDSEL

ADDR

MSIZE

DATA

TAR

SYNC

TAR

11712212

Firmware Hub Interface

The FWH Interface features:

s

a five Signal Communication Interface (FWH0-

FWH4) to support the Read and Write

operations,

s

five General Purpose Inputs (FGPI0-FGPI4) for

platform design flexibility,

s

four Identification Inputs (ID0-ID3) to address

up to 16 different memory devices,

s

a Register Based Block Locking and a

Hardware Block Protection for firmware

security.

It has an Input Clock (CLK) synchronized with the

33MHz PCI clock and a 3.3V Input/Output bus.

Figure 1 shows the pin description for FWH

interface mode.

There are two different protection modes designed

for the FWH interface. The hardware protection

has the Top Block Lock (TBL) that prevents the

Top Block from being changed, and the Write

Protect (WP) that prevents all the other blocks

from being changed.

Figure 4. Address/Address Multiplexed

Interface Configuration

AI03796

11

G

DQ0-

DQ7

VCC

M50FW040

RC

VSS

8

IC

RP

RB

W

A0-A10

VPP