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bring the chip-sets into synchronization. Figure 2

shows the Firmware Hub Read Protocol and

Figure 3 shows the Firmware Hub Write Protocol.

Address/Address Multiplexed Interface

The

Address/Address

Multiplexed

Interface

features:

s

11 Address Inputs for Row/Column

addressing,

s

8 Data Inputs/Outputs for data bus operation,

s

Output Enable for Read operation,

s

Write Enable for Programming operation,

s

Row/Column Address Select (RC) for Row or

Column Address Latch

s

Ready/Busy Output for verify operation.

Figure 4 shows the pin description for A/A Mux

interface mode.

The software protection is a register based read

and write protection in FWH interface mode. The

registers can be altered to set the appropriate

Locking to protect against piracy. Depending on

the degree of protection required, the Lock

Registers can set the memory in either Read Lock,

Write Lock or Lock Down mode .

The Firmware Hub protocol is Intel proprietary and

is based on the Low Pin Count Interface (LPC).

Four Signal Communication pins (FWH0 – FWH3)

together with an Input Communication Frame

(FWH4) are used to determine the bus operation.

A four bit Cycle Type (CYCLETYPE) defines

whether it is Reading or Writing to the FWH.

The Device Select bits (IDSEL) indicate which

FWH device is selected. The Memory Size Cycle

(MSIZE) always gives 0000 (single byte transfer).

The Turn Around bits (TAR), occupying two clock

cycles, are driven by the host when it is turning

control over to the peripheral and driven by the

peripheral when it is turning control over to the

host. Synchronize bits (SYNC) are required to

Figure 5. Address/Address Multiplexed Interface Read Protocol

AI03406

tAVAV

tCLAX

tCHAX

tGLQX

tGLQV

tGHQX

VALID

A0-A10

G

DQ0-DQ7

RC

tCHQV

tGHQZ

COLUMN ADDR VALID

W

RP

tPHAV

ROW ADDR VALID

NEXT ADDR VALID

tAVCL

tAVCH