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WM8602SEDS/V 数据表(PDF) 11 Page - Wolfson Microelectronics plc |
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WM8602SEDS/V 数据表(HTML) 11 Page - Wolfson Microelectronics plc |
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11 / 46 page  Product Preview WM8602 w PP Rev 1.5 May 2004 11 CONTROL INTERFACE TIMING – 3-WIRE MODE CSB SCLK SDIN t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 60 ns SCLK pulse cycle time tSCY 80 ns SCLK pulse width low tSCL 30 ns SCLK pulse width high tSCH 30 ns SDIN to SCLK set-up time tDSU 20 ns SCLK to SDIN hold time tDHO 20 ns CSB pulse width low tCSL 20 ns CSB pulse width high tCSH 20 ns CSB rising to SCLK rising tCSS 20 ns Pulse width of spikes that will be suppressed tps 2 8 ns Table 6 Control Interface Timing – 3-Wire Serial Control Mode |
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