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IC-HTP 数据表(PDF) 21 Page - IC-Haus GmbH

部件名 IC-HTP
功能描述  DUAL CW P-TYPE LASER DIODE DRIVER
PDF  51 Pages
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制造商  ICHAUS [IC-Haus GmbH]
网页  http://www.ichaus.biz
标志 ICHAUS - IC-Haus GmbH

IC-HTP 数据表(HTML) 21 Page - IC-Haus GmbH

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iC-HTP
DUAL CW P-TYPE LASER DIODE DRIVER
Rev B1, Page 21/51
Register
Address Bits Default Description
INITRAM
0x00
0
R/O RAM initialized.
PDOVDD
0x00
1
R/O Power down event at VDD
MEMERR
0x00
2
R/O RAM memory validation error
OVT
0x00
3
R/O Overtemperature event
OVC2
0x00
4
R/O Overcurrent at channel 2
OVC1
0x00
5
R/O Overcurrent at channel 1
OSCERR
0x00
6
R/O Oscillator error (watchdog set)
CFGTIMO
0x00
7
R/O Configuration mode timeout event
MAPC1
0x01
0
R/O Channel 1 current state
MONC1
0x01
1
R/O Monitor channel 1 enabled at least once (latched)
LDASAT1
0x01
2
R/O Channel 1 LDA saturation event
PDOVBL1
0x01
3
R/O Power down event at VBL1 or VBL1 not equal to VBL2 in merge mode
MAPC2
0x01
4
R/O Channel 2 current state
MONC2
0x01
5
R/O Monitor channel 2 enabled at least once (latched)
LDASAT2
0x01
6
R/O Channel 2 LDA saturation event
PDOVBL2
0x01
7
R/O Power down event at VBL2 or Power down in any of VBL1 or VBL2 in merge mode
Table 46: Status registers overview
In order to enable the channels, the error events must
be acknowledged. Acknowledging an error is accom-
plished by reading the STATUS register. After a pow-
er-on PDOVDD, PDOVBL1, PDOVBL2 and INITRAM
errors will be set, therefore it is required to read STA-
TUS0 and STATUS1 registers after each power-on.
Exiting standby mode will not reset the RAM but will
set the PDOVDD status bit. Therefore STATUS0 must
be read once after each standby to re-enable the laser
channels.
In case of an overcurrent (OVC) or an overtemperature
(OVT) event, laser channels are disabled.
A memory error event and a configuration timeout er-
ror event will also disable the laser channels. More
information about the memory error on page 38. The
conditions to enable each laser channel are shown in
figure 9.
7
PDOVBL2
(Addr. 0x01)
(Addr. 0x00)
5
6
1
4
STATUS0
0
PDOVDD
MEMERR
(Addr. 0x10 )
Pin
OVC2
CFGTIMO
(Addr. 0x15 )
Pin
3
INITRAM
OVT
OVC1
2
7
PDOVBL1
STATUS1
0
1
1
2
3
4
5
6
1
1
&
DISC2
INSOPEN
EMCOPEN
EC2
DISC1
EC1
MAPC2
MAPC1
&
1
&
1
1
1
&
1
Figure 9: Laser control logic in MCU mode



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