AD7911AUJ-R2 datasheet(18/28 Pages) AD

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AD7911/AD7921

Rev. 0 | Page 18 of 28

MODES OF OPERATION

The two modes of operation of the AD7911/AD7921 are

normal mode and power-down mode. The mode of operation is

selected by controlling the logic state of the CS signal. The point

at which CS is pulled high after the conversion has been initi-

ated determines whether the AD7911/AD7921 enter power-

down mode. Similarly, if already in power-down mode, CS can

control whether the device returns to normal operation or

remains in power-down mode.

Power-down mode is designed to provide flexible power

management options and to optimize the ratio of power

dissipation to throughput rate for different application

requirements.

NORMAL MODE

Normal mode is intended for the fastest throughput rate

performance. The user does not have to worry about any

power-up time, because the AD7911/AD7921 remain fully

powered all the time. Figure 26 shows the operation of the

AD7911/AD7921 in this mode.

The conversion is initiated on the falling edge of CS, as

described in the Serial Interface section. To ensure that the part

remains fully powered up at all times, CS must remain low until

at least 10 SCLK falling edges have elapsed after the falling edge

of CS. If CS is brought high any time after the 10th SCLK falling

edge but before the end of tCONVERT, the part remains powered-

up, but the conversion is terminated and DOUT goes back into

three-state. For the AD7911/AD7921, a minimum of 14 and

16 serial clock cycles, respectively, are needed to complete the

conversion and access the complete conversion result.

CS can idle high until the next conversion or can idle low until

CS returns high sometime prior to the next conversion

(effectively idling CS low). Once a data transfer is complete

(DOUT has returned to three-state), another conversion can be

initiated after the quiet time, tQUIET, has elapsed by bringing CS

low again.

POWER-DOWN MODE

Power-down mode is intended for use in applications where

slower throughput rates are required. Either the ADC is

powered down between each conversion, or a series of

conversions can be performed at a high throughput rate and

then the ADC is powered down for a relatively long duration

between these bursts of several conversions. When the

AD7911/AD7921 are in power-down mode, all analog circuitry

is powered down.

To enter power-down mode, the conversion process must be

interrupted by bringing CS high any time after the second

falling edge of SCLK and before the 10th falling edge of SCLK,

as shown in Figure 27. Once CS has been brought high in this

window of SCLKs, then the part enters power-down mode, the

conversion that was initiated by the falling edge of CS is

terminated, and DOUT goes back into three-state. If CS is

brought high before the second SCLK falling edge, then the part

remains in normal mode and does not power down. This helps

to avoid accidental power-down due to glitches on the CS line.

To exit this mode of operation and power the AD7911/AD7921

up again, a dummy conversion is performed. On the falling edge

of CS, the device begins to power up and continues to power up

as long as CS is held low until after the falling edge of the 10th

SCLK. The device is fully powered up once 16 SCLKs have

elapsed and valid data results from the next conversion, as

shown in Figure 28. If CS is brought high before the 10th falling

edge of SCLK, then the AD7911/AD7921 go back into power-

down mode. This helps to avoid accidental power-up due to

glitches on the CS line or an inadvertent burst of 8 SCLK cycles

while CS is low. Therefore, although the device might begin to

power up on the falling edge of CS, it powers down again on the

rising edge of CS, as long as this occurs before the 10th SCLK

falling edge.

AD7911/AD7921

SCLK

DIN

DOUT

CHANNEL FOR NEXT CONVERSION

CONVERSION RESULT

Figure 26. Normal Mode Operation

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