AD7921AUJ-R2 datasheet(24/28 Pages) AD

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AD7911/AD7921

Rev. 0 | Page 24 of 28

APPLICATION HINTS

GROUNDING AND LAYOUT

The printed circuit board that houses the AD7911/AD7921

should be designed such that the analog and digital sections are

separated and confined to certain areas of the board. This

facilitates the use of ground planes that can be separated easily.

A minimum etch technique is generally best for ground planes,

because it gives the best shielding. Digital and analog ground

planes should be joined at only one place. If the AD7911/

AD7921 is in a system where multiple devices require an

AGND-to-DGND connection, the connection should still be

made at one point only, a star ground point that should be

established as close as possible to the AD7911/AD7921.

Avoid running digital lines under the device, because these

couple noise onto the die. The analog ground plane should be

allowed to run under the AD7911/AD7921 to avoid noise

coupling. The power supply lines to the AD7911/AD7921

should use as large a trace as possible to provide low impedance

paths and reduce the effects of glitches on the power supply line.

Fast-switching signals like clocks should be shielded with digital

ground to avoid radiating noise to other sections of the board,

and clock signals should never be run near the analog inputs.

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other to

reduce the effects of feedthrough through the board. A micro-

strip technique is by far the best, but is not always possible with

a double-sided board. In this technique, the component side of

the board is dedicated to ground planes, while signals are placed

on the solder side.

Good decoupling is also very important. The analog supply

should be decoupled with 10 µF tantalum in parallel with 0.1 µF

capacitors to AGND. To achieve the best performance from

these decoupling components, the user should endeavor to keep

the distance between the decoupling capacitor and the VDD and

GND pins to a minimum with short track lengths connecting

the respective pins.

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