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AT75C310 数据表(PDF) 3 Page - ATMEL Corporation |
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AT75C310 数据表(HTML) 3 Page - ATMEL Corporation |
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3 / 12 page ![]() AT75C310 3 Memory Timing Waveforms Figure 2. DRAM Read Cycle (Single Read) Table 1. DRAM Read Cycle (Single Read) Timings Symbol Parameter Min (ns) Max (ns) tRC Read or Write Cycle Time 125.0 – t RAS RAS Pulse Width 82.0 – t RP RAS Precharge Time 42.0 – tCSH CAS Hold Time 61.0 – t CRP CAS to RAS Precharge Time 49.0 – t RCD RAS to CAS Delay Time 41.0 – tRSH RAS Hold Time 29.0 – t CAS CAS Pulse Width 20.0 – t ASR Row Address Setup Time 1.0 tRAH Row Address Hold Time 22.0 t ASC Column Address Setup Time 15.0 t CAH Column Address Hold Time 21.0 tCAC Access Time from CAS – 22.0 t OEA Access Time from NDOE – 34.0 t AA Access Time from Column Address – 38.0 tRAC Access Time from RAS – 63.0 t OHO Data Hold from NDOE 0 – tOHO tAA tRAC tOEA tCAC tRC tRP tRAS tRCD tRSH tCSH tCRP tCAS tCAH tASC tRAH tASR D NDOE A NCASx NRASx |
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