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4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

The Status and Control Bits

WIP bit

The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register

progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress,

when

WIP

bit

sets

0,

means

the

device

is

not

in

program/erase/write status register progress.

WEL bit

The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal

Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register,

Program or Erase instruction is accepted.

SEC, TB, BP2, BP1, BP0 bits

The Block Protect (SEC, TB, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Program

and Erase instructions. These bits are written with the Write Status

Register instruction. When the Block Protect (SEC, TB, BP2, BP1, BP0) bits are set to 1,the relevant memory

area(as defined in Table 6 and Table 7).becomes protected against Page Program, Sector Erase and Block

Erase instructions. The Block Protect (SEC, TB, BP2, BP1, BP0) bits can be written provided that the

Hardware Protected mode has not been set.

SRP1, SRP0 bits

The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The

SRP bits control the method of write protection: software protection, hardware protection, power supply lock-

down or one time programmable protection.

QE bit

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation.

When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE pin is set to 1, the

Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI

operation if the /WP or /HOLD pins directly to the power supply or ground).

LB3/LB2/LB1 bit

The LB bit is a non-volatile One Time Program (OTP) bit in Status Register that provide the write protect

control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked.

LB can be set to 1 individually using the Write Register instruction. LB is

One Time Programmable, once it’s set

to 1, the 256byte Security Registers will become read-only permanently, LB3/2/1 for Security Registers 3:1.

CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register2 (bit6). It is used in conjunction the SEC-

BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection

table for details. The default setting is CMP=0.

SUS bit

The SUS bit is a read only bit in the status register2 (bit7) that is set to 1 after executing an Erase/Program

Suspend (75H) instruction. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) instruction as well as

a power-down, power-up cycle.