ECT25S40 datasheet(32/46 Pages) E-CMOS

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E-CMOS Corp. (www.ecmos.com.tw)

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4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

Sector Erase (20H)

The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable

instruction must previously have been executed to set the Write Enable Latch bit.The Sector

Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-address

byte on SI. Any address inside the sector is a valid address for the Sector Erase instruction.

/CS must be driven low for the entire duration of the sequence.

See Figure 28, The Sector Erase instruction sequence: /CS goes low sending 64KB Block

Erase instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth

bit of the last address byte has been latched in; otherwise the Sector Erase instruction is not

executed. As soon as /CS is driven high, the self-timed Sector Erase cycle (whose duration is

tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read

to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified

time before the cycle is completed, the Write Enable Latch bit is reset. A Sector Erase

instruction applied to a sector which is protected by the Block Protect (SEC, TB, BP2, BP1,

BP0) bit is not executed.

Figure 28. Sector Erase Sequence Diagram

32KB Block Erase (52H)

The 32KB Block

Erase instruction is for erasing the all data of the chosen block. A Write

Enable instruction must previously have been executed to set the Write Enable Latch bit. The

32KB Block Erase instruction is entered by driving /CS low, followed by the instruction code,

and 3-byte address on SI. Any address inside the block is a valid address for the 32KB Block

Erase instruction. /CS must be driven low for the entire duration of the sequence.

See Figure 29, the 32KB Block Erase instruction sequence: /CS goes low sending 32KB

Block Erase instruction 3-byte address on SI /CS goes high. /CS must be driven high after the

eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase

instruction is not executed. As soon as /CS is driven high, the self-timed Block Erase cycle

(whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status

Progress

(WIP)

bit

during

the self-timed Block Erase cycle, and is 0 when it is

completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit

is reset. A 32KB Block Erase instruction applied to a block which is protected by the Block

Protect (SEC, TB, BP2, BP1, BP0) bits (see

Table 6&7) is not executed.

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