AD7656ABSTZ datasheet(7/29 Pages) AD

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AD7656A

Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter

Rating

VDD to AGND, DGND

0 V to +16.5 V

VSS to AGND, DGND

0 V to −16.5 V

VDD to AVCC

AVCC + 0.7 V to 16.5 V

AVCC to AGND, DGND

−0.3 V to +7 V

DVCC to AVCC

−0.3 V to AVCC + 0.3 V

DVCC to DGND, AGND

−0.3 V to +7 V

AGND to DGND

−0.3 V to +0.3 V

VDRIVE to DGND

−0.3 V to DVCC + 0.3 V

Analog Input Voltage to AGND

VSS + 1 V to VDD − 1 V

Digital Input Voltage to DGND

−0.3 V to VDRIVE + 0.3 V

Digital Output Voltage to DGND

−0.3 V to VDRIVE + 0.3 V

REFIN/REFOUT to AGND

−0.3 V to AVCC + 0.3 V

Input Current to Any Pin Except Supplies1

±10 mA

Operating Temperature Range

−40°C to +85°C

Storage Temperature Range

−65°C to +150°C

Junction Temperature

150°C

Pb/Sn Temperature, Soldering

Reflow (10 sec to 30 sec)

240(0)°C

Pb-Free Temperature, Soldering Reflow

260(0)°C

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

POWER SUPPLY SEQUENCING

Simultaneous application of VDD and VSS is necessary to

guarantee reliability of the device. In the cases where

simultaneous application cannot be guaranteed, VDD must power

up before VSS. When a negative voltage is applied to the analog

inputs before VDD and VSS are fully powered up, a 560 Ω resistor

must be placed on the analog inputs.

A number of sequencing combinations can lead to temporary

high current states; however, when all supplies are powered up,

the device returns to normal operating currents. The analog

input (AIN) coming before AVCC causes temporary high current

on the analog inputs. Digital inputs before DVCC, and DVCC

before other supplies, also cause temporary high current states.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages. These

specifications apply to a 4-layer board.

Table 4. Thermal Resistance

Package Type

θJA

θJC

Unit

64-Lead LQFP

°C/W

ESD CAUTION

Rev. 0 | Page 6 of 28

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