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AD7656A

Data Sheet

Changing the Analog Input Range (H/S SEL = 0)

The AD7656A RANGE pin allows the user to select either ±2 ×

VREF or ±4 × VREF as the analog input range for the six analog

inputs. When the H/S SEL pin is low, the logic state of the

RANGE pin is sampled on the falling edge of the BUSY signal

to determine the range for the next simultaneous conversion.

When the RANGE pin is logic high at the falling edge of the

BUSY signal, the range for the next conversion is ±2 × VREF.

When the RANGE pin is logic low at the falling edge of the

BUSY signal, the range for the next conversion is ±4 × VREF.

After a RESET pulse, the range is updated on the first falling

BUSY edge after the RESET pulse.

Changing the Analog Input Range (H/S SEL = 1)

When the H/S SEL pin is high, the range can be changed by

writing to the control register. Bits[DB12:DB10] in the control

conversion. Each analog input pair has an associated range bit,

allowing independent ranges to be programmed on each ADC

pair. When the RNGx bit is set to 1, the range for the next

conversion is ±2 × VREF. When the RNGx bit is set to 0, the

range for the next conversion is ±4 × VREF.

Serial Interface (SER/PAR/SEL = 1)

By pulsing one, two, or all three CONVST x signals, the AD7656A

use their on-chip trimmed oscillator to simultaneously convert

the selected channel pairs on the rising edge of CONVST x.

After the rising edge of CONVST x, the BUSY signal goes high

to indicate that the conversion has started. It returns low when

the conversion is complete 3 µs later. The output register is

loaded with the new conversion results, and data can be read

from the AD7656A. To read the data back from the device over

the serial interface, tie SER/PAR high. The CS and SCLK signals

are used to transfer data from the AD7656A. The device has three

DOUT x pins: DOUT A, DOUT B, and DOUT C. Data can be

read back from the device using one, two, or all three DOUT x

lines.

Figure 26 shows six simultaneous conversions and the read

sequence using three DOUT x lines. Also in Figure 26, 32 SCLK

transfers are used to access data from the AD7656A; however,

two 16 SCLK individually framed transfers with the CS signal

can also be used to access the data on the three DOUT x lines.

When the serial interface is selected and the conversion data

clocks out on all three DOUTx lines, tie DB0/SEL A, DB1/SEL B,

and DB2/SEL C to VDRIVE. These pins are used to enable the

DOUT A to DOUT C lines, respectively.

If it is required to clock conversion data out on two data out lines,

use DOUT A and DOUT B. To enable DOUT A and DOUT B,

tie DB0/SEL A and DB1/SEL B to VDRIVE and tie DB2/SEL C low.

When six simultaneous conversions are performed and only two

DOUT x lines are used, a 48 SCLK transfer can be used to

access the data from the AD7656A. The read sequence is shown

in Figure 27 for a simultaneous conversion on all six ADCs

using two DOUT x lines. If a simultaneous conversion occurred

on all six ADCs, only two DOUT x lines are used to read the

results from the AD7656A. DOUT A clocks out the result from

V1, V2, and V5, and DOUT B clocks out the results from V3,

V4, and V6.

Data can also be clocked out using just one DOUT x line, in which

case, use DOUT A to access the conversion data. To configure the

AD7656A to operate in this mode, tie DB0/SEL A to VDRIVE and

tie DB1/SEL B and DB2/SEL C low. The disadvantage of using

only one DOUT x line is that the throughput rate is reduced.

Data can be accessed from the AD7656A using one 96-SCLK

transfer, three 32-SCLK individually framed transfers, or six 16-

SCLK individually framed transfers. In serial mode, tie the RD

signal low. Leave the unused DOUT x line(s) unconnected in serial

mode.

CONVST A,

CONVST B,

CONVST C

BUSY

DOUT A

DOUT B

DOUT C

SCLK

tQUIET

tACQ

tCONVERT

Figure 26. Serial Interface with Three DOUT x Lines

Rev. 0 | Page 20 of 28

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