STV7620S/M/F

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CIRCUIT DESCRIPTION

STV7620S/M/F includes all the logic and power

circuits necessary to drive the Plasma Display

Panel (PDP) column of electrodes. Binary values

of each pixel of the displayed line are loaded into

the shift register by a 6 bit wide (A1 - A6) data bus.

Data is shifted at each low to high transition of the

CLK clock.

The forward /reverse (F/R) input is used to select

the direction of the shift register.

The maximum frequency of the shift clock is

40MHz. This leads to an equivalent 240 MHz seri-

al shift register for a 6 x 16 bits arrangement.

When the STB signal is Low, data are transferred

from the shift register to the latch and the power

output stages.

All the output data are kept memorised and held in

the latch stage when the latch input STB is pulled

high.

Vsssub and Vsslog must be connected as close as

possible to the logical reference ground of the ap-

plication.

STV7620S/M/F is supplied with a 5 V power sup-

ply. All the logic inputs can be driven either by 5V

CMOS logic or by 3.3V CMOS logic.

A low EMI function has been implemented: the fall-

ing edge of the outputs has 2 slopes, a smooth

one followed by a steeper one.

The smooth slopes width increases from 20ns for

the fast version to 55ns for the slow version what-

ever the external load.

Table 1: Shift register truth table

Table 2: Power output truth table

Qn+1 = A1, Qn+2 = A2, Qn+3 = A3, Qn+4 = A4, Qn+5 = A5, Qn+6 = A6, n = [0,6,12,18,...,90]

Input

Shift register function

F/R

CLK

Output Q

L

rise

Forward shift

L

H or L

Steady

H

rise

Reverse shift

H

H or L

Steady

X

X

6 bits shift register

Qn

STB

BLK

POC

Driver Output

Comments

X

X

L

X

all L

Output at low level

X

X

H

L

all H

Output at high level

X

H

H

H

Qn

Data latched

L

L

H

H

L

Data copied

H

L

H

H

H

Data copied