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AD6652PCB 数据表(PDF) 7 Page - Analog Devices

部件名 AD6652PCB
功能描述  12-Bit, 65 MSPS IF to Baseband Diversity Receiver
PDF  76 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6652PCB 数据表(HTML) 7 Page - Analog Devices

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AD6652
Rev. 0 | Page 7 of 76
ELECTRICAL CHARACTERISTICS
AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 5.
Parameter (Conditions)
Temp
Test Level
Min
Typ
Max
Unit
LOGIC INPUTS
Logic Compatibility
Full
IV
3.3 V CMOS
Logic 1 Voltage
Full
IV
2.0
V
Logic 0 Voltage
Full
IV
0.8
V
Logic 1 Current
Full
IV
−10
+10
µA
Logic 0 Current
Full
IV
−10
+10
µA
Input Capacitance
25°C
V
4
pF
LOGIC OUTPUTS
Logic Compatibility
Full
IV
3.3 V CMOS/TTL
Logic 1 Voltage (VOH) (IOH = 0.25 mA)
Full
IV
2.4
VDDIO − 0.2
V
Logic 0 Voltage (VOL) (IOL = 0.25 mA)
Full
IV
0.2
0.4
V
SUPPLY CURRENTS
Narrow Band (150 kHz BW) (61.44 MHz CLK)
Four Individual Channels
IAVDD
25°C
II
160
200
215
mA
IVDD
25°C
II
240
280
300
mA
IVDDIO
25°C
II
25
40
45
mA
CDMA (1.25MHz BW) (61.44 MHz CLK) Example1
IAVDD
25°C
V
200
mA
IVDD
25°C
V
336
mA
IVDDIO
25°C
V
68
mA
WCDMA (5 MHz BW) (61.44 MHz CLK) Example1
IAVDD
25°C
V
200
mA
IVDD
25°C
V
330
mA
IVDDIO
25°C
V
89
mA
TOTAL POWER DISSIPATION
Narrow Band (150 kHz BW) (61.44 MHz CLK)
Four Individual Channels
25°C
II
1.2
1.5
1.6
W
CDMA (61.44 MHz)1
25°C
V
1.7
W
WCDMA (61.44 MHz)1
25°C
V
1.7
W
ADC in Standby and DDC in Sleep Mode2
25°C
V
2.3
mW
1 All signal processing stages and all DDC channels active.
2 ADC standby power measured with ACLK inactive.



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