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CS61577-IP1 数据表(PDF) 36 Page - List of Unclassifed Manufacturers

部件名 CS61577-IP1
功能描述  T1/E1 LINE INTERFACE
PDF  44 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

CS61577-IP1 数据表(HTML) 36 Page - List of Unclassifed Manufacturers

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applications. A letter at the intersection of a row
and column in Table 2 indicates that the selected
transformer is supported for use with the device.
The transformer is installed in the evaluation
board with pin 1 positioned to match the letter
illustrated on the drawing in Table 2. For exam-
ple, the Pulse Engineering PE-65388 transformer
may be used with the transmitter of the CS61575
device for 100
Ω T1 applications only (as indi-
cated by note 3) when installed in transformer
socket T1 with pin 1 at position D (upper right).
PROTOTYPING AREA
A prototyping area with power supply and ground
connections is provided on the evaluation board.
This area can be used to develop and test a vari-
ety of additional circuits like a data pattern gener-
ator, CS2180B framer, system synchronizer PLL,
or specialized interface logic.
EVALUATION HINTS
1. Properly terminate TTIP/TRING when evaluat-
ing the transmit output signal. For more informa-
tion concerning pulse shape evaluation, refer to
the Crystal application note entitled "Measure-
ment and Evaluation of Pulse Shapes in T1/E1
Transmission Systems."
2. Change the receiver terminating resistors R9
and R10 when evaluating E1 applications. Resis-
tors R9 and R10 should be replaced with 240
resistors for terminating 120
Ω E1 twisted-pair
lines or 150
Ω resistors for terminating 75Ω E1
coaxial lines. Two 243
Ω resistors and two 150Ω
resistors are included with the evaluation board
for this purpose.
3. Closing a DIP switch on S2 towards the label
sets the device control pin of the same name to
logic 1 (+5 Volts).
4. To avoid damage to the external host controller
connected to JP1, all S2 switch positions (except
CLKE) should be open. In the Host operating
mode, the CLKE switch selects the active edge of
SCLK and RCLK.
LINE INTERFACE EVALUATION BOARD
36
DS40DB3



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