2003 Jun 25

2

Philips Semiconductors

Product specification

Octal D-type transparent latch; 3-state

74ALVC573

FEATURES

• Wide supply voltage range from 1.65 to 3.6 V

• Complies with JEDEC standards:

JESD8-7 (1.65 to 1.95 V)

JESD8-5 (2.3 to 2.7 V)

JESD8B/JESD36 (2.7 to 3.6 V).

• 3.6 V tolerant inputs and outputs

• CMOS low power consumption

• Direct interface with TTL levels (2.7 to 3.6 V)

• Power-down mode

• Latch-up performance exceeds 250 mA

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

DESCRIPTION

The 74ALVC573 is a high-performance, low-power,

low-voltage, Si-gate CMOS device and superior to most

advanced CMOS compatible TTL families.

The 74ALVC573 is an octal D-type transparent latch

featuring separate D-type inputs for each latch and 3-state

outputs for bus oriented applications. A latch enable (LE)

input and an output enable (OE) input are common to all

internal latches.

The 74ALVC573 consists of eight D-type transparent

latches with 3-state true outputs. When LE is HIGH, data

at the Dn inputs enters the latches. In this condition the

latches are transparent, i.e. a latch output will change state

each time its corresponding D-input changes.

When LE is LOW the latches store the information that

was present at the D-inputs a set-up time preceding the

HIGH-to-LOW transition of LE. When OE is LOW, the

contents of the 8 latches are available at the outputs.

When OE is HIGH, the outputs go to the high-impedance

OFF-state. Operation of the OE input does not affect the

state of the latches.

The 74ALVC573 is functionally identical to the

74ALVC373, but the has a different pin arrangement.

QUICK REFERENCE DATA

Notes

N = total load switching outputs;

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

propagation delay input Dn to output Qn

2.5

ns

ns

ns

ns

input capacitance

3.5

pF

power dissipation capacitance per buffer

outputs enabled

37

pF

outputs disabled

7

pF