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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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PCI7620 数据表(PDF) 6 Page - Texas Instruments |
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PCI7620 数据表(HTML) 6 Page - Texas Instruments |
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6 / 248 page  vii 7.13 Power Management Capabilities Pointer Register 7–9 . . . . . . . . . . . . . . . 7.14 Interrupt Line Register 7–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.15 Interrupt Pin Register 7–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.16 Minimum Grant and Maximum Latency Register 7–11 . . . . . . . . . . . . . . . . . 7.17 OHCI Control Register 7–11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.18 Capability ID and Next Item Pointer Registers 7–12 . . . . . . . . . . . . . . . . . . . 7.19 Power Management Capabilities Register 7–13 . . . . . . . . . . . . . . . . . . . . . . 7.20 Power Management Control and Status Register 7–14 . . . . . . . . . . . . . . . . 7.21 Power Management Extension Registers 7–14 . . . . . . . . . . . . . . . . . . . . . . . 7.22 PCI Miscellaneous Configuration Register 7–15 . . . . . . . . . . . . . . . . . . . . . . 7.23 Link Enhancement Control Register 7–16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.24 Subsystem Access Register 7–17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.25 GPIO Control Register 7–18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OHCI Registers 8–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 OHCI Version Register 8–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 GUID ROM Register 8–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Asynchronous Transmit Retries Register 8–6 . . . . . . . . . . . . . . . . . . . . . . . 8.4 CSR Data Register 8–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 CSR Compare Register 8–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 CSR Control Register 8–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 Configuration ROM Header Register 8–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 Bus Identification Register 8–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9 Bus Options Register 8–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 GUID High Register 8–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 GUID Low Register 8–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12 Configuration ROM Mapping Register 8–11 . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13 Posted Write Address Low Register 8–11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14 Posted Write Address High Register 8–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.15 Vendor ID Register 8–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16 Host Controller Control Register 8–13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.17 Self-ID Buffer Pointer Register 8–14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.18 Self-ID Count Register 8–15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.19 Isochronous Receive Channel Mask High Register 8–16 . . . . . . . . . . . . . . 8.20 Isochronous Receive Channel Mask Low Register 8–17 . . . . . . . . . . . . . . . 8.21 Interrupt Event Register 8–18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.22 Interrupt Mask Register 8–20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.23 Isochronous Transmit Interrupt Event Register 8–22 . . . . . . . . . . . . . . . . . . 8.24 Isochronous Transmit Interrupt Mask Register 8–23 . . . . . . . . . . . . . . . . . . . 8.25 Isochronous Receive Interrupt Event Register 8–24 . . . . . . . . . . . . . . . . . . . 8.26 Isochronous Receive Interrupt Mask Register 8–25 . . . . . . . . . . . . . . . . . . . 8.27 Initial Bandwidth Available Register 8–25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.28 Initial Channels Available High Register 8–26 . . . . . . . . . . . . . . . . . . . . . . . . 8.29 Initial Channels Available Low Register 8–26 . . . . . . . . . . . . . . . . . . . . . . . . . 8.30 Fairness Control Register 8–27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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