AX−SFAZ, AX−SFAZ−API

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4

Table 1. PIN FUNCTION DESCRIPTIONS

Description

Type

Pin(s)

Symbol

CLKP

40

A

TCXO interface

GND

Center pad

P

Ground on center pad of QFN, must be connected

A = analog input

I = digital input signal

O = digital output signal

PU = pull−up

I/O = digital input/output signal

N = not to be connected

P = power or ground

PD = pull−down

All digital inputs are Schmitt trigger inputs, digital input

and output levels are LVCMOS/LVTTL compatible. Pins

GPIO[3:0] must not be driven above VDD_IO, all other

digital inputs are 5 V tolerant. All GPIO pins and UARTRX

start up as input with pull−up. For explanations on how to

use the GPIO pins, see chapter “AT Commands”.

Table 2.

Pin

Possible GPIO Modes

GPIO0

0, 1, Z, U, A, T

GPIO1

0, 1, Z, U, A

GPIO4

0, 1, Z, U, T

GPIO5

0, 1, Z, U

GPIO6

0, 1, Z, U

GPIO7

0, 1, Z, U

GPIO8

0, 1, Z, U

GPIO9

0, 1, Z, U

0 = pin drives

1 = not to be connected

Z = pin is high impedance input

U = pin is input with pull−up

A = pin is analog input

T = pin is driven by clock or DAC

Pinout Drawing

Figure 2. Pinout Drawing (Top View)

AX−SFAZ / AX−SFAZ−API

QFN40

8

7

6

5

4

3

2

1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

40

39

38

37

36

35

34

33

32

31

30

29

VDD_ANA

ANTP

GND

ANTN

ANTP1

GND

GND

VDD_ANA

GND

RESET_N

GPIO9

UARTTX

UARTRX

RXLED

TXLED

NC