MCP6021 datasheet(13/28 Pages) MICROCHIP

13 / 28 page

 2003 Microchip Technology Inc.

DS21685B-page 13

MCP6021/2/3/4

To use the internal mid-supply reference for an

inverting gain circuit, connect the VREF pin to the non-

inverting input, as shown in Figure 3-4. The capacitor

CB helps reduce power supply noise on the output.

FIGURE 3-4:

Inverting gain circuit using

VREF (MCP6021 and MCP6023 only).

If you don’t need the mid-supply reference, leave the

VREF pin open.

3.5

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases, and the closed loop bandwidth is

reduced. This produces gain-peaking in the frequency

response, with overshoot and ringing in the step

response.

When driving large capacitive loads with these op

amps (e.g., > 60 pF when G = +1), a small series

resistor at the output (RISO in Figure 3-5) improves the

feedback loop’s phase margin (stability) by making the

load resistive at higher frequencies. The bandwidth will

be generally lower than the bandwidth with no

capacitive load.

FIGURE 3-5:

Output resistor RISO

stabilizes large capacitive loads.

Figure 3-6 gives recommended RISO values for

different capacitive laods and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

gain are equal. For inverting gains, GN is 1+|Gain| (e.g.,

-1 V/V gives GN = +2 V/V).

FIGURE 3-6:

Recommended RISO values

for capacitive loads.

After selecting RISO for your circuit, double-check the

resulting frequency response peaking and step

response overshoot. Evaluation on the bench and

simulations with the MCP6021/2/3/4 Spice macro

model are very helpful. Modify RISO’s value until the

response is reasonable.

3.6

Supply Bypass

With this family of operational amplifiers, the power

supply pin (VDD for single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good, high-frequency performance. It also needs a

bulk capacitor (i.e., 1 µF or larger) within 100 mm to

provide large, slow currents. This bulk capacitor can be

shared with other parts.

3.7

PCB Surface Leakage

In applications where low input bias current is critical,

PCB (printed circuit board) surface-leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012

Ω. A 5V difference would

cause 5 pA of current to flow, which is greater than the

MCP6021/2/3/4 family’s bias current at 25°C (1 pA,

typ).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in Figure 3-7.

FIGURE 3-7:

Example guard ring layout.

VIN

VOUT

VREF

VIN

MCP602X

RISO

VOUT

100

1,000

100

1,000

10,000

Normalized Capacitance; CL/GN (pF)

Guard Ring

VIN–VIN+

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