Data Sheet

AD7321

Rev. B | Page 9 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

AD7321

14

13

12

11

10

9

8

DGND

DOUT

SCLK

TOP VIEW

(Not to Scale)

DIN

DGND

AGND

REFIN/OUT

CS

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7321 and frames the serial data transfer.

2

DIN

Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the

register on the falling edge of SCLK (see the Registers section).

3, 13

DGND

Digital Ground. Ground reference point for all digital circuitry on the AD7321. The DGND and AGND

voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a

transient basis.

4

AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7321. All analog input signals

and any external reference signal should be referred to this AGND voltage. The AGND and DGND

voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a

transient basis.

5

REFIN/OUT

Reference Input/Reference Output. The on-chip reference is available on this pin for external use to the

AD7321. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor

should be placed on the reference pin (see the Reference section). Alternatively, the internal reference

is disabled, and an external reference is applied to this input. On power-up, the external reference

mode is the default condition.

6

Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.

7, 8

Analog Input 0 to Analog Input 1. The analog inputs are multiplexed into the on-chip track-and-hold.

The analog input channel for conversion is selected by programming the Channel Address Bit ADD0 in

the control register. The inputs are configured as two single-ended inputs, one true differential input

pair, or one pseudo differential input. The configuration of the analog inputs is selected by programming the

mode bits, Bit Mode 1 and Bit Mode 0, in the control register. The input range on each input channel is

controlled by programming the range register. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V are

selected on each analog input channel when a +2.5 V reference voltage is used (see the Registers section).

9

Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.

10

Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7321.

This supply should be decoupled to AGND.

11

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface

12

DOUT

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits

are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The

data stream consists of two ZERO bits, a channel identification bit, the sign bit, and 12 bits of conversion

data. The data is provided MSB first (see the Serial Interface section).

14

SCLK

Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the

AD7321. This clock is also used as the clock source for the conversion process.