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Data Sheet

AD7321

Rev. B | Page 33 of 36

APPLICATION HINTS

LAYOUT AND GROUNDING

The printed circuit board that houses the AD7321 should be

designed so that the analog and digital sections are confined to

certain areas of the board. This design facilitates the use of

ground planes that can easily be separated.

To provide optimum shielding for ground planes, a minimum

etch technique is generally best. All AGND pins on the AD7321

should be connected to the AGND plane. Digital and analog

ground pins should be joined in only one place. If the AD7321

is in a system where multiple devices require an AGND and

DGND connection, the connection should still be made at only

one point. A star point should be established as close as possible

to the ground pins on the AD7321.

Good connections should be made to the power and ground

planes. This is done with a single via or multiple vias for each

supply and ground pin.

Avoid running digital lines under the AD7321 device because

this couples noise onto the die. However, the analog ground

plane should be allowed to run under the AD7321 to avoid

noise coupling. The power supply lines to the AD7321 device

should use as large a trace as possible to provide low impedance

paths and reduce the effects of glitches on the power supply line.

To avoid radiating noise to other sections of the board, com-

ponents, such as clocks, with fast switching signals should be

shielded with digital ground and never run near the analog inputs.

Avoid crossover of digital and analog signals. To reduce the effects

of feedthrough within the board, traces should be run at right

angles to each other. A microstrip technique is the best method,

but its use may not be possible with a double-sided board. In

this technique, the component side of the board is dedicated

to ground planes, and signals are placed on the other side.

Good decoupling is also important. All analog supplies should

be decoupled with 10 µF tantalum capacitors in parallel with

0.1 µF capacitors to AGND. To achieve the best results from

these decoupling components, they must be placed as close as

possible to the device, ideally right up against the device. The

0.1 µF capacitors should have a low effective series resistance

(ESR) and low effective series inductance (ESI), such as is

typical of common ceramic and surface mount types of

capacitors. These low ESR, low ESI capacitors provide a low

impedance path to ground at high frequencies to handle

transient currents due to internal logic switching.

POWER SUPPLY CONFIGURATION

It is recommended that Schottky diodes be placed in series with

the AD7321 VDD and VSS supply signals. Figure 53 shows this

Schottky diode configuration. BAT43 Schottky diodes are used.

VIN0

VIN1

VDD

VSS

V+

V–

SCLK

DOUT

DIN

VCC

3V/5V

NOTES

1. ADDITIONAL PINS

OMITTED FOR CLARITY.

AD7321

Figure 53. Schottky Diode Connection

In an application where non-symmetrical VDD and VSS supplies

are being used, adhere to the following guidelines. Table 16

outlines the VSS supply range that can be used for particular VDD

voltages when non-symmetrical supplies are required. When

operating the AD7321 with low VDD and VSS voltages, it is

recommended that these supplies be symmetrical.

Table 16. Non-Symmetrical VDD and VSS Requirements

VDD

Typical VSS Range

5 V

−5 V to −5.5 V

6 V

−5 V to −8.5 V

7 V

−5 V to −11.5 V

8 V

−5 V to −15 V

9 V

−5 V to −16.5 V

10 V to 16.5 V

−5 V to −16.5 V

For the 0 to 4 × VREF range, VSS can be tied to AGND as per

minimum supply recommendations outlined in Table 6.

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