AD7277ARMZ datasheet(10/28 Pages) AD

10 / 28 page

AD7276/AD7277/AD7278

Data Sheet

Rev. D | Page 10 of 28

TIMING EXAMPLES

For the AD7276, if CS is brought high during the 14

th SCLK rising

edge after the two leading zeros and 12 bits of the conversion

have been provided, the part can achieve the fastest throughput

rate, 3 MSPS. If CS is brought high during the 16

th SCLK rising

edge after the two leading zeros and 12 bits of the conversion

and two trailing zeros have been provided, a throughput rate of

2.97 MSPS is achievable. This is illustrated in the following two

timing examples.

Timing Example 1

In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz and the

throughput is 3 MSPS. This produces a cycle time of t2 +

12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns minimum and

tACQ = 67 ns.

This satisfies the requirement of 60 ns for tACQ. Figure 6 also

shows that tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where

t8 = 14 ns max. This allows a value of 43 ns for tQUIET, satisfying

the minimum requirement of 4 ns.

Timing Example 2

The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz,

and the throughput is 2.97 MSPS. This produces a cycle time of

t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns minimum and

tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + t8 +

tQUIET, where t8 = 14 ns max. This satisfies the minimum

requirement of 4 ns for tQUIET.

SCLK

SDATA

THREE-STATE

THREE-

STATE

2 LEADING

ZEROS

2 TRAILING

ZEROS

tCONVERT

ZERO

DB11

DB10

DB9

DB1

DB0

ZERO

tQUIET

1/THROUGHPUT

Figure 5. AD7276 Serial Interface Timing Diagram

tQUIET

tCONVERT

1/THROUGHPUT

234

SCLK

SDATA

THREE-STATE

THREE-

STATE

2 LEADING

ZEROS

ZZERO

DB11

DB10

DB9

DB1

DB0

Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle

SCLK

tCONVERT

tQUIET

1/THROUGHPUT

12.5(1/fSCLK)

tACQUISITION

Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle

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