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AD7927 数据表(PDF) 13 Page - Analog Devices |
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AD7927 数据表(HTML) 13 Page - Analog Devices |
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13 / 29 page ![]() AD7927 Data Sheet Rev. D | Page 12 of 28 CONTROL REGISTER The control register on the AD7927 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7927 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on the DIN line corresponds to the AD7927 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 5. Table 5. Control Register Bit Functions MSB LSB WRITE SEQ DONTC ADD2 ADD1 ADD0 PM1 PM0 SHADOW DONTC RANGE CODING Table 6. Control Register Bit Function Description Bit Mnemonic Description 11 WRITE The value written to this bit of the control register determines whether the following 11 bits are loaded to the control register. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, then the remaining 11 bits are not loaded to the control register and it remains unchanged. 10 SEQ The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer function and access the shadow register (see Table 10). 9 DONTC Don’t care. 8 to 6 ADD2 to ADD0 These three address bits are loaded at the end of the present conversion and select which analog input channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as described in Table 9. The selected input channel is decoded as shown in Table 7. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data (see the Serial Interface section). The next channel to be converted on is selected by the mux on the 14th SCLK falling edge. 5, 4 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7927 as shown in Table 8. 3 SHADOW The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer function and access the shadow register (see Table 10). 2 DONTC Don’t care. 1 RANGE This bit selects the analog input range to be used on the AD7927. If it is set to 0, the analog input range extends from 0 V to 2 × REFIN. If it is set to 1, the analog input range extends from 0 V to REFIN (for the next conversion). For the 0 V to 2 × REFIN range, AVDD = 4.75 V to 5.25 V. 0 CODING This bit selects the type of output coding the AD7927 uses for the conversion result. If this bit is set to 0, the output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next conversion). Table 7. Channel Selection ADD2 ADD1 ADD0 Analog Input Channel 0 0 0 VIN0 0 0 1 VIN1 0 1 0 VIN2 0 1 1 VIN3 1 0 0 VIN4 1 0 1 VIN5 1 1 0 VIN6 1 1 1 VIN7 Table 8. Power Mode Selection PM1 PM0 Mode 1 1 Normal Operation. In this mode, the AD7927 remains in full power mode, regardless of the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the AD7927. 1 0 Full Shutdown. In this mode, the AD7927 is in full shutdown mode with all circuitry on the AD7927 powering down. The AD7927 retains the information in the control register while in full shutdown. The part remains in full shutdown until these bits are changed. 0 1 Auto Shutdown. In this mode, the AD7927 automatically enters full shutdown mode at the end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 μs and the user should ensure that 1 μs has elapsed before attempting to perform a valid conversion on the part in this mode. 0 0 Invalid Selection. This configuration is not allowed. |
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