REV. A

AD7675

–15–

BUSY

CS, RD

CNVST

SYNC

SCLK

SDOUT

12

3

14

15

16

D15

D14

D2

D1

D0

X

EXT/

INT = 0

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

Figure 17. Master Serial Data Timing for Reading (Read after Convert)

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

D15

D14

D2

D1

D0

X

12

3

14

15

16

BUSY

SYNC

SCLK

SDOUT

CS, RD

CNVST

EXT/

INT = 0

Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

SERIAL INTERFACE

The AD7675 is configured to use the serial interface when the

SER/

PAR is held high. The AD7675 outputs 16 bits of data,

MSB first, on the SDOUT pin. This data is synchronized with

the 16 clock pulses provided on the SCLK pin.

MASTER SERIAL INTERFACE

Internal Clock

The AD7675 is configured to generate and provide the serial

data clock SCLK when the EXT/

INT pin is held low. The AD7675

also generates a SYNC signal to indicate to the host when the

serial data is valid. The serial clock SCLK and the SYNC signal

can be inverted if desired. The output data is valid on both the

rising and falling edge of the data clock. Depending on RDC/

SDIN input, the data can be read after each conversion, or

during the following conversion. Figure 17 and Figure 18 show

the detailed timing diagrams of these two modes.

Usually, because the AD7675 has a longer acquisition phase

than the conversion phase, the data is read immediately after

conversion. That makes the mode master, read after conversion,

the most recommended serial mode when it can be used.