FEATURES
2-21 mm body size
Package height down to 0.5 mm
High die count pure memory, eMMC, eMCP and MCP
Design, assembly and test capabilities that enable stacking of DRAM with logic or flash memory devices
Logic/Flash, digital/analog and other ASIC/memory combinations of 320 I/O and greater
Established package infrastructure with standard CABGA footprints
Consistent product performance, high yields and reliability
JEDEC standard outlines including MO-192 and MO-219
Thin DA film and spacer technology, FoW and FoD
Extended die overhang wirebonding
Low loop wirebonding less than 35 μm
Vacuum transfer and compression molding
Wafer thinning/handling to 25 μm
Pb-free, RoHS compliant and green materials
Passive component integration options

Applications
SCSP is the best solution to address a range of design requirem ents, including:
Higher memory capacity and more efficient memory architectures
Smaller, lighter and more innovative product form factors
Lower cost and more space efficiency