TDA7333

6/21

The architecture is a very economical implementation because digital multipliers are not required. It is imple-

mented by cascading 4 integrators operating at full sampling rate (XTI/2) followed by 4 differentiators operating

at the reduced sampling rate (XTI/2/16). Also wrap around logic is allowed and the internal overflow will not af-

fect the output signal as long as a minimum required bit width is maintained.

The transfer function of this Sinc4/16 filter is:

with K = 4, M = 16

and its frequency response is:

with

Figure 4. Transfer function of a 4th order Sinc Filter, decimation factor is 16.

Hz

()

1

M

-----

1z M

–

–

1z 1

–

–

--------------------





 K

=

Hejω

()

1

M

-----

M

ω

2

---------





sin

ω

2

----





sin

-----------------------









 K

=

ω

2

π f

fs

-----

=

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

x 10

6

100

90

80

70

60

50

40

30

20

10

0

Sinc4/16 Transfer Function

Frequency [Hz]