TDA7333

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(3) select sensitivity of quality bit.

00: minimum (reset value)

11: maximum

Note :

Sinc4reg and testreg are reserved registers dedicated to testing and evaluation.

select PLL’s time constants by software or hardware:

1: software. Time constants are selected by pllb[1:0] resp.

pllf

0: hardware. (reset value) Time constants automatically

increase after a reset.

set the 57kHz pll time constant (1)

bit 0 of 1187.5Hz pll time constant (2)

bit 1 of 1187.5Hz pll time constant (2)

bit 0 of quality sensitivity (3)

bit 1 of quality sensitivity (3)

select oscillator frequency:

1: 8.664MHz

0: 8.55MHz (reset value)

bitname

access

bit7

bit 0

bit1

bit2

bit 3

bit4

bit5

bit6

r

r/w

r/w

r/w

r/w

r/w

r/w

r/w

shw

-

pllb1

freq

qsens0

qsens1

pllb0

pllf

pllb1

1

0

0

0

pllb0

10

1

1

(2)

locktimeneededfor90degdeviation

5ms(resetstatus)

15ms

35ms

76ms

resetvalue

1

0

00

00

0

0

pllf

(1)

0

1

locktimeneededfor90degdeviation

2ms

10ms

rds_bd_ctrl