TDA7333

12/21

Note : when changing the interrupt mode, one has to

perform a reset of the module (i.e set the bit “ar_res” at

one)

(3) qu[3..0] is a counter of the quality bit information coming

from the RDS demodulator. It is counting the number of bits

which are marked as bad by the demodulator. Only those bits

are allowed to be corrected. Thus the quality bit counter indi-

cates the maximum possible number of bits being corrected.

interrupt bit. It is set to one on every programmed interrupt. It

is reset by reading rds_int register.

interrupt source

itsrc[2:0] select the interrupt source (1)

synchronization information.

1: the module is already synchronized.

0: the module is synchronizing

It is used to force a resynchronization. If it is set to one, the

RDS modules are forced to resynchronization state.

The bit is automatically reset. So it is always read as zero.

RDS block.

if 1, one block has been detected

rds_int and rds_bd_ctrl write order (when in SPI mode)

1: rds_int and rds_bd_ctrl are updated with data shifted in.

0: rds_int and rds_bd_ctrl are not updated.

It indicates if the error correction was successfull.

1: the syndrome was zero after the error correction.

0: the syndrome did not become zero and therefore the

correction was not successfull.

1: a block E is detected.This indicates a paging block

which is defined in the RBDS specification used in the

united states of America.

0: an ordinary RDS block A, B, C, c´or D is detected, or no

valid syndrome was found.

bit 0 of block counter (2)

bit 1 of block counter (2)

bit 0 of quality counter

(3)

bit 1 of quality counter

(3)

bit 2 of quality counter

(3)

bit 3 of quality counter

(3)

bitname

access

bit7

bit0

bit1

bit2

bit3

bit4

bit5

bit6

r

r/w

rr/w

r

r/w

r/w

r/w

itsrc0

int

ar_res

bne

itsrc1

synch

write

resetvalue

0

00

0

0

00

0

itsrc2

(1)

itsrc2

0

0

itsrc1

interruptsource

itsrc0

blockB

blockA

blockD

TA

TAEON

nointerrupt

0

0

10

0

11

1

10

1

11

1

01

rds_int

RDSBlock

0

01

bit name

access

bit 7

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

r

r

rr

rr

r

r

synz

e

qu0

qu3

qu1

qu2

blk1

blk0

blk1

1

0

0

0

blk0

block A

block name

block D

1

block C,C'

0

block B

1

1

(2)

reset value

0

0

00

00

0

0

rds_qu